The invention is generally related to very large scale integrated circuits. More particularly, the invention is related to compensating for voltage transients in very large scale integrated circuits.
As silicon technology is scaled down in integrated circuit (xe2x80x9cICxe2x80x9d) design, the voltage at which the integrated circuit operates is also reduced. However, power consumption tends to increase for the scaled down ICs, increasing the current going through the power supply and the power delivery network.
Because of this large amount of current in integrated circuits, such as, for example, very large scale integrated (xe2x80x9cVLSIxe2x80x9d) circuits used for microprocessor design, a large transient may occur in the power supply network due to switching events and instantaneous changes in the current function. This change in the current may cause the voltage to vary by a large percentage of the supply. A reduction in the operating voltage due to the change in current is known as a xe2x80x9cvoltage droopxe2x80x9d. Voltage droops may cause delays in circuit operation.
Traditionally, processors and most VLSI circuits operate at a fixed frequency, such as, for example, 1 GHz. Because of the frequency is fixed, the VLSI circuits should maintain the frequency of operation for the lowest voltage point that may be seen in the circuit. Thus, a voltage droop may require a VLSI circuit to operate at lower frequency than it could support if the frequency were based on the average voltage of operation.
A method for compensating for voltage droop in an integrated circuit is described. The method may include detecting a voltage droop in an integrated circuit driven by a clock signal and determining an optimum frequency change to compensate for the voltage droop. The method may further include adapting cycle time of the clock signal in an incremental manner to achieve the optimum frequency change.
An integrated circuit having voltage droop compensation capability is also described. The integrated circuit may include a plurality of chip circuits, a clock control system, a clock distribution network including at least one delay element and a voltage droop detector. In one embodiment, the clock control system may adapt cycle time in the clock distribution network through use of the at least one delay element when a voltage droop is detected.